1. Field Of The Invention
The present invention relates to an electronic component manufactured using an anodic junction and a method of manufacturing the electronic component and, more particularly, to an electrical contact between a wire and an electrode with an insulating layer surrounding each electrode on a semiconductor chip surface, an electrically conductive surface of each wire being anodically bonded when the wire is simultaneously pressure-joined and connected to an electrode on the semiconductor chip surface.
2. Description Of The Related Art
FIG. 39 is a perspective view showing electrodes 2 attached to a surface of a semiconductor chip 1, according to a conventional ultrasonic thermocompression wire bonding method, connected through gold wires 5 to inner leads 4 extending from lead frames, not shown. FIG. 40 is a diagrammatic illustration of one end of the gold wire connected to the electrode 2 on the semiconductor chip 1 by ultrasonic thermocompression bonding.
In FIG. 40, the semiconductor chip 1 is fixedly secured through a die bonding material 6 to a die pad 41. The die bonding material 6 and the die pad 41 can withstand the pressure from a capillary 7 when a ball 51 at the tip of the gold wire 5 is connected to the electrode 2 by ultrasonic thermocompression bonding and, further, to support the semiconductor chip 1. In the ultrasonic thermocompression wire bonding method, the tip of the gold wire 5 passing through the capillary 7 is turned into the ball 51 by means of a high-voltage discharge. Subsequently, the ball 51 is pressed against the electrode 2 on the semiconductor chip 1 and subjected to ultrasonic vibration and heat, whereby it is ultrasonically thermocompression-bonded to the electrode 2, as indicated at 52 in the same illustration. Further, the capillary 7 is moved to the position of the tip of the inner lead 4 before being lowered to couple the tip of the inner lead 4 to the gold wire 5.
FIGS. 41A, 41B, and 42 are illustrations of a structure of a lead frame with the electrodes 2 coupled through the gold wires 5 to the tips of the inner leads 4 in accordance with a conventional ultrasonic thermocompression wire bonding method. In FIG. 41A, a frame 3 is integral with eight die pads 41, not shown, and thirty-six inner leads 4, not shown. FIG. 41B is an enlarged view showing a portion indicated by X in FIG. 41A. In FIG. 41B, the frame 3 has thirty-six inner leads 4 at its inside portion, a die pad 41 supported by suspending leads 42 at the central portion of the frame, and external leads 44 at its circumferential portion. FIG. 42 is an illustration of the detailed structure of the thirty-six inner leads 4, die pad 41, and suspending leads 42. In the same illustration, a rectangle indicated by a broken line is representative of a position that is encapsulated with a molding resin. FIG. 43 is a cross-sectional view showing a semiconductor device completed such that the electrode 2 is connected through the gold wire 5 to the inner lead 4 by ultrasonic thermocompression wire bonding before the frame 3 is encapsulated with a molding resin 8. In the same illustration, reference numeral 53 designates a contact portion between the inner lead 4 and the gold wire 5 due to the ultrasonic thermocompression bonding. FIG. 44 is an enlarged view showing a pressure-bonded portion between an electrode, not shown, and the inner lead 4 on the chip 1, and FIG. 45 is an illustration of the deformation of the ball 51 when the ball 51 is ultrasonically thermocompression-bonded onto the electrode 2 on a surface of the semiconductor chip 1. When the electrode 2 is an aluminum electrode, the gold wire 5 and the deformed is ball portion 52 both consist of the same gold wire material at the time of completion of the ultrasonic thermocompression bonding, while an alloy of gold and aluminum is formed as a pressure-bonded layer 54 with the aluminum electrode. Reference numeral 2i depicts an electrically insulating passivation film (which will be referred to hereinafter as an electrically insulating film) attached to the semiconductor chip 1 at a position other than the electrode 2.
FIG. 46 illustrates a deformed ball portion 52 of the gold wire 5 pressed against the electrode 2 by means of the capillary 7 in the completed connection. FIG. 47 shows the other end of the gold wire 5 stitch-bonded to the inner lead 4 by the capillary 7 and its deformed portion 53 pressed against the tip of the inner lead 4. In FIG. 47, although the material of the deformed portion 53 stitch-bonded to the inner lead 4 depends upon the lead frame material, when an iron frame is used, it is silver plated, and hence an alloy layer made of gold and silver is produced on the stitch side. For this reason, the alloy layer 54 of gold is present, as shown in FIG. 45, but has been omitted in FIG. 47.
FIGS. 48A to 48E are illustrations for describing processes taken when the inner lead 4 is connected through the gold wire 5 to an electrode on the semiconductor chip 1 according to the conventional ultrasonic thermocompression wire bonding technique. In FIG. 48A, heat is transferred from a heating block 9 through the die pad 41 to the chip 1 by heat conduction. The tip of the gold wire 5 leading from the tip of the capillary 7 is formed into a ball by a high voltage power supply torch 10. FIG. 48B shows the capillary 7 lowered toward the electrode 2 (omitted from the illustration) so that the formed ball 51 is pressure-bonded to the electrode under ultrasonic vibration and pressure. FIG. 48C illustrates the capillary 7 through which the gold wire 5 passes moved toward the inner lead 4 in order for the other end of the gold wire 5 to be connected to the inner lead 4 after ultrasonic thermocompression bonding of the ball 51 is completed, as shown in FIG. 45. FIG. 48D is illustrative of the other end of the gold wire 5 stitch-bonded to the inner lead 4, and FIG. 48E is illustrative of the other end of the gold wire 5 pressure-attached to the inner lead 4 by the stitch bonding in the state as shown in FIG. 47, before the gold wire 5 is held and lifted by a clamp 11 of the capillary 7, to be cut off at the stitch bonded portion.
FIG. 49 is a plan view of a semiconductor chip 1 produced such that the electrode 2 and the inner lead 4 are coupled through the gold wire 5 to each other by means of ultrasonic thermocompression bonding. FIG. 50 illustrates nineteen electrodes 2 on the semiconductor chip 1 wherein reference numeral 2i designates an electrically insulating film attached to a portion other than the electrodes 2 on the semiconductor chip 1. The electrode 2 has dimensions C.times.E and the electrically insulating film 2i has dimensions B.times.D, larger than the dimensions of the electrode 2, and hence the boundary between the electrode 2 and the electrically insulating film 2i appears so that the electrode 2 is exposed as shown in FIG. 51. The cross-sectional structure of the semiconductor chip 1 is such that the electrically insulating film 2i overlaps the circumferential portion of the electrode 2, as shown in FIG. 45. As illustrated in FIG. 51, in order to increase the electrical and mechanical degree of coupling of the gold wire 5, the area of the electrode 2 should be larger than the circumferential area of the deformed ball 52 when the ball 51 is ultrasonically thermocompression-bonded.
Depending upon the accuracy of the wire bonding apparatus, the dimension A between the electrodes 2 as shown in FIG. 51 is determined taking the circumferential dimension of the deformed ball 52 and other factors into consideration. In general, as long as the ultrasonic thermocompression bonding is made, the width of the electrode 2 to be wire-bonded should be larger than the width of the circuit wiring 21 in FIG. 51. Further, in the case of the conventional wire bonding method, the semiconductor device should be designed on the basis of dimensions I, J, K, and L as shown in FIG. 52 while taking into account the accuracy and performance of the wire bonding.
FIG. 53 is a cross-sectional view taken along the axis where the gold wire 5 shown in the plan view of FIG. 52 extends between the electrode 2 and the inner lead 4. Whether the dimension of the gold wire 5 relative to the corner portion of the semiconductor chip 1 is satisfactory can be known by checking the dimension I. The space between the corner of the die pad 41 and the gold wire 5 can be confirmed on the basis of the dimension J and the relationship between the die pad 41 and the inner lead 4. In addition, dimension K must be confirmed to know whether there is sufficient dimension to the stitch bonding 53.
FIG. 54A is a perspective view showing the inner structure of a completed semiconductor device (integrated circuit) in which the inner lead 4 is connected through the gold wire 5 to the electrode 2 located at the central portion of the chip 1 according to the ultrasonic thermocompression wire bonding method. FIG. 54B is a cross-sectional view taken along line 54B--54B in FIG. 54A. FIG. 55A is a cross-sectional view of a conventional TAB package. In the same illustration, numeral 21 represents an electrode bump formed on a tape carrier electrode lead (which will be referred hereinafter to as an electrode lead) 4b through thermocompression bonding. FIG. 55B is an enlarged view showing the contact portion of the electrode with the electrode bump 21. In the TAB system, the connection between the electrode of the semiconductor chip 1 and the electrode lead 4a is made through the electrode bump 21, thus accomplishing electrical coupling between the electrode and the electrode lead 4a.
FIG. 56 is an illustration for describing one example of a method of anodically bonding a silicon semiconductor body (member) with an electrically insulating material (member), as disclosed in Japanese Patent Publication No. 53-28747. In FIG. 56, a semiconductor material la is placed on a resistance heating strip 67 that is energized by a power supply A. Onto a surface of the semiconductor material la there is attached a glass film 1b, an insulating coating (for example, boro-silicate glass made of boric acid and silicic acid) which shows a slight electrical conductivity when heated. Further, numeral 68 designates an electrically insulating material which is layered on and with the semiconductor material 1a with the insulating film 1b interposed therebetween, and numeral 65 denotes a pressure connecting piece for lightly pressing the electrically insulating material 68 against the semiconductor material 1a. Further, a positive electrode terminal 63 of a direct-current power supply 60 is connected to the resistance heating strip 67 for causing a positive current to flow from the semiconductor material 1a to the electrically insulating material 68, while the negative electrode terminal is connected with the pressure connecting piece 65.
Next, a description is given of the anodic bonding method. The semiconductor material 1a is heated through the resistance heating strip 67 to the extent that the insulating coating 1b is slightly electrically conductive (to approximately 400 to 700 degrees, depending upon the insulating material). As a result, a small positive current (for example, several .mu.A/mm.sup.2) flows for about one minute from the semiconductor material 1a to the electrically insulating material 68, whereby an anodically grown oxide junction is formed at the boundary between the semiconductor material 1a and the electrically insulating material 68, thus completing the anodic bonding between the semiconductor material 1a and the electrically insulating material 68.
At this time, the electrically insulating material 68 is not melted by the heating temperature or the applied current. The heating is only for giving an electrically conductive property to the insulating coating 1b. The junction between the semiconductor material 1a and the electrically insulating material 68 can be achieved only with the positive current flowing from the semiconductor material 1a to the electrically insulating material 68.
FIG. 57 is an illustration for describing one example of a method of anodically bonding two semiconductor materials 1c and 1d made of silicon with an electrically insulating material 68, as disclosed again in Japanese Patent Publication No. 53-28747. In this method, the two semiconductor materials 1c and 1d whose surfaces are attached to the insulating coating 1b are placed on the electrically insulating material 68 which, in turn, is mounted on the resistance heating strip 67. The semiconductor materials 1c and 1d are respectively equipped with direct-current power supplies 61 and 62 for causing positive currents to flow, and the positive electrode terminals of the direct-current power supplies 61 and 62 are connected to the corresponding semiconductor materials 1c and 1d, respectively, while the negative electrode terminals are connected in common to the resistance heating strip 67.
Furthermore, in the anodic bonding method, the resistance heating strip 67 heats the semiconductor materials 1c and 1d through the electrically insulating material 68 so that the insulating coating 1b has a slight electrical conductivity. As a result, a small positive current (for example, several .mu.A/mm.sup.2) flows for about one minute from the semiconductor materials 1c and 1d to the electrically insulating material 68, whereby an anodically grown oxide junction is formed at the boundary between the semiconductor materials 1c and 1d and the electrically insulating material 68, thus completing the junction between the semiconductor materials 1c and 1d and the electrically insulating material 68.
As examples of general applications of the anodic bonding method disclosed in other publications, Japanese Patent Application No. 1-185242 and Publication No. 4-164841 disclose a method wherein the rear surface of a silicon wafer is used as an electrically conductive surface which, in turn, is bonded to a glass wafer. Japanese Patent Publication No. 53-28747 exemplifies, as a semiconductor, a junction between silicon and quartz, a junction between silicon and boro-silicate glass made of boric acid and silicic acid, a heat resistant glass having a low expansion coefficient, a junction between germanium and a boro-silicate glass, and a junction between silicon and sapphire.
Moreover, as an example of special applications, Japanese Patent Publication No. 63-117233 discloses a method of anodically bonding a silicon wafer with a silicon supporting wafer in a capacitance-type pressure sensor. A detailed description of the principle of the anodic bonding method will be omitted here as it is given in the Japanese Patent Publication No. 53-28747 and others.
FIG. 58 is a plan view showing a conventional laminated multi-layer insulating substrate, and FIG. 59 is a cross-sectional perspective view showing the longitudinal structure of FIG. 58. In FIG. 58, numeral 70 designates a laminated multi-layer insulating substrate, numeral 71 depicts an insulating plate, and 76 stands for a wiring pattern on the insulating plate 71. Further, in FIG. 59, numerals 71 to 75 indicate five stacked insulating plates, and numerals 76 to 81 and the black-colored portions represent wiring patterns on the insulating plates 71 to 75, respectively. For formation of the laminated multi-layer insulating substrate 70 by stacking the insulating plates 71 to 75 on top of each other, lead wires are inserted into through-holes in the insulating plates 71 to 75 and electrically coupled to the wiring of the insulating plates 71 to 74 stacked on each other.
The joining methods of the conventional technology were described above in the following order: the wire bonding method, the bump junction method using TAB, and the anodic bonding method. The anodic bonding method has been known as a means of coating a chip surface with an insulating film as well as bonding a silicon strain gauge with a base used for stress relaxation in a pressure sensor.
In conventional anodic bonding, the silicon to be bonded to a glass insulating plate has some degree of rigidity and, for the junction, a glass insulating plate, which also has the same degree of rigidity as the silicon, is used.
In the foregoing description, the wire bonding method must include 1) formation of the ball, 2) heating, application of pressure, and supply of ultrasonic vibration in the ultrasonic thermocompression bonding, 3) movement of the capillary, 4) ultrasonic thermocompression bonding of the stitch portion, and 5) practicing the five processes for cutting the gold wire for each inner lead. In the bump junction by TAB, 1) heating and compression bonding, and 2) the moving process are repeated for each of the electrode junctions. Collective bonding is still not put into practice. In these bonding methods, the electrode and the electrode to be electrically connected to each other, i.e., a metallic conductor and a metallic conductor, are made to be joined with each other by ultrasonic thermocompression bonding or thermocompression bonding. For this reason, the mechanical strength of the portions to be electrically connected to each other, for example, the shear strength, depends upon the state of the bonded portions.
In addition, the portions that are ultrasonically thermocompression-bonded or thermocompression-bonded due to metal contact and frictional heating and the applied load produce an alloy layer. Accordingly, a safe strength cannot be ensured except where the area of the junction is large. For instance, when the diameter of the gold wire is .phi.=25 .mu.m, the diameter .phi. of the contact surface of the junctioned portion is set to .phi.=100 .mu.m; that is, the diameter is four times and the area is sixteen times that of the gold wire.
The following problems arise with the conventional contact methods for the electrode and the inner lead.
a) In the conventional method in which the connection between the electrode and the inner lead is made through a gold wire having an extremely low rigidity, it is necessary to provide mechanical strength to both end portions of the gold wire to be electrically connected, so that the dimension of the connected portion needs to exceed the value necessary for the electrical connection. As a result, the dimensions of the electrodes on the chip must be large, which goes against the object of increasing the density of integrated circuits (IC). This is an obstacle to miniaturizing IC chips.
b) In the prior method wherein the junction between the inner lead and the electrode is made through a member such as the gold wire having an extremely low rigidity, it is necessary that the semiconductor chip and the inner lead be encapsulated in order to protect both end portions of the gold wire and the gold wire itself against external loads or to protect the semiconductor chip against the external environment. Accordingly, increasing the outer dimensions of the semiconductor device to a given value is unavoidable.
c) Because of the recent higher integration of ICs, the number of electrodes is increasing. However, in the conventional wire bonding method or bump junction method by TAB, in order to ensure mechanical strength, the dimension of the electrode needs to be increased, with the result that the dimension of the entire chip depends upon the number of electrodes, thus presenting a barrier to miniaturizing IC chips.
d) In cases where the number of connection pins exceeds one hundred, even if the connection accuracy varies because the joining work is carried out for each of the electrodes, difficulty is experienced in checking whether the contacts with the electrodes are normal.
e) Since it is difficult to know an accurate value of the mechanical strength of the alloy layer made at the junction by ultrasonic thermocompression bonding or thermocompression bonding, it is necessary to design the bonded portion with a high safety factor. For this reason, a sufficient over-design is required, taking into account vibration during the assembly process, empty weight, and other external forces, and hence a limitation on designing occurs.
f) In a conventional electrode connecting method, the connecting work needs to be repeatedly done the same number of times as the number of electrodes or twice the number of electrodes. For this reason, as the number of the pins in the semiconductor device increases, the time required for making the connections increases.